job description
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PhD thesis on efficient multi-band InP and CMOS millimeter wave front ends
Project
Communication networks are the cornerstone of the digital transformation of our societies and economies. The Netherlands is strong in RF semiconductor technology and mobile technology applications for 4G and 5G mobile networks. 6G, the next generation of technology in the 2030s, offers the Netherlands a huge economic opportunity to extend this position to areas of the global 6G value chain that have earlier shifted to Asian and US companies. Securing this position is critical for the Netherlands to maintain control of its mobile network. In the Future Network Services (FNS) program, leading ICT and semiconductor companies and research institutes will work together on specific parts of 6G: software antennas, AI-driven network software and leading 6G applications. By integrating these components at the 6G software layer, FNS creates a powerful approach to make 6G a truly intelligent network. This innovation provides an important boost to the Dutch economy and sustainable profitability through advanced industrial activities and significant export opportunities. It will make 6G networks more energy efficient and drive digital autonomy.
Outline of the FNS-6G program:
The FNS Innovation Program is divided into four program lines: (1) Smart Components, developing software antennas for the new high frequencies of 6G (millimeter-wave and terahertz); (2) Smart Networks, developing AI-driven software for the 6G radio and core network; (3) Leading Applications, developing new 6G applications in the mobility, energy, health, and other industries to create value through new settings in the industry value chain; and (4) Strengthening the ecosystem, integrating FNS innovations into national 6G testbeds, incentivizing startups and SMEs, developing and implementing a human capital agenda, and ensuring policy harmonization. The Alliance currently consists of 60 large and small telecom, semiconductor and ICT companies, universities and public institutions.
PhD position “Efficient multi-band InP millimeter-wave front-ends, including integration possibilities with CMOS”:
Wireless communications have experienced explosive growth to date. Over the last 30 years, after five generations of wireless systems, data rates have increased by several orders of magnitude. In addition, wireless communications offer a very wide range of content to support a variety of applications. 6G networks are the next step in the evolution of wireless communications. 6G networks will aim to increase data rates, reduce latency, greatly improve security, and ultimately combine communications and sensing systems.
To meet these challenges, the operating frequency needs to be increased to the millimeter-wave portion of the spectrum in order to use a wide signal bandwidth. In addition, devices will need to operate in multiple frequency bands and support different operating frequencies.
The use of millimeter-wave carrier frequencies provides benefits in terms of signal bandwidth. As a result, the data rate of the communication system and the resolution of the sensing devices are improved. However, this poses a challenge in meeting link budget requirements due to high path loss. Conventional transmitter and receiver architectures designed and implemented using CMOS technology are unable to meet link budget specifications. They have limited gain, noise and output power capabilities at millimeter-wave frequencies. In addition, thermal and integration issues are encountered when using these architectures in beamforming and multiple-input multiple-output (MIMO) solutions. An alternative is the use of Indium Phosphide (InP) technology, which significantly improves the performance of millimeter-wave circuits. Therefore, CMOS and InP chips need to be effectively combined/integrated to maximize integration. This is critical for beamforming and multiple-input multiple-output (MIMO) solutions, especially in the case of multi-band operation.
The goal of this PhD project is to investigate millimeter-wave transceiver architectures taking into account the optimal distribution of building blocks between CMOS and InP chips as well as multi-band operation. In addition, it is necessary to study the topology of the implementation of millimeter-wave building blocks in InP technology (power amplifiers, low-noise amplifiers, mixers) in order to maximize the efficiency, reduce the occupied chip area, enable multi-band operation and increase the possibilities of integration with CMOS. Integration schemes need to be scrutinized. The most promising options need to be selected in terms of cost, robustness and complexity. Finally, the scope of the prototype needs to be defined for proof of concept. The prototypes need to include InP and CMOS chips as well as integration solutions. The prototypes need to be characterized and the results compared with simulation results.
The main responsibilities of the PhD student are
In-depth study of millimeter-wave transceiver architectures, taking into account integration between CMOS and InP chips as well as multi-band operation. Propose the most promising architectures.
In-depth study of integration techniques/solutions between CMOS and InP chips. Propose optimal integration techniques/solutions in terms of cost, robustness and complexity.
In-depth study of millimeter-wave InP building blocks (power amplifiers, LNAs, mixers). Propose the most promising topologies in terms of efficiency, chip area and multi-band operation.
Define prototypes for proof of concept, design, fabricate and characterize prototypes.
Perform theoretical studies and simulations, validation/comparison through characterization and testing.
Contribute to the knowledge of the scientific community by publishing high quality papers.
Write and defend a PhD thesis summarizing research results.
offer requirements
Master’s degree in Electrical Engineering.
Strong background in electronic circuit design.
Experience with IC design/simulation/implementation tools such as Cadence, Virtuoso, Spectre, ADS.
Familiarity with EM software tools such as EMX, Momentum for chip passive structure design, and CST and HFSS for package design and integrated solution evaluation.
Excellent analytical and problem solving skills.
Effective communication and collaboration skills.
We select based on the following general requirements:
Formal requirements regarding prior education: you should have earned a Master of Science degree from a recognized institution of higher education.
Distinction: You should have a grade point average of at least eight (10). In addition, you should have scored at least 8 (10) points in your M.Sc. thesis.
English: You should have good communication skills (written and oral) in English. Please provide TOEFL/IELTS scores if available.
Originality: Your MSc dissertation or later work (publication) should reflect some original ideas. Critical and independent thinking is important.
Team player: you should be able to work well in a team with other program members.
offer benefits/salary
A rewarding career in a dynamic and ambitious university, in an interdisciplinary environment and within an international network. You will work on a beautiful green campus within walking distance of the central train station. In addition, we offer you
Full-time employment for four years, with a mid-term evaluation (go/no-go) after nine months. 10% of your working time is dedicated to teaching duties.
Salary and benefits (e.g. pension scheme, paid pregnancy and maternity leave, partially paid parental leave) in accordance with the Dutch Universities Collective Labor Agreement at level P (minimum €2,901, maximum €3,707).
8.3% year-end bonus and 8% annual leave pay.
High-quality training programs and other support to help you develop into a self-aware, autonomous scientific researcher. At TU/e, we encourage you to learn on your own.
State-of-the-art technical infrastructure, on-campus nursery and sports facilities.
Subsidized commuting, work-from-home and internet costs.
Employee immigration panel and tax compensation program for international candidates (30% facilitation).